Interrupt aggregator

Maturity simulatedTargets FPGA + ASICDifficulty EasyPriority 1

Aggregates N interrupt sources with per-source level or rising-edge mode, sticky pending bits with write-1-to-clear and software set, an enable mask, a combined irq output and the highest-priority (lowest-numbered) pending source id.

Simulated. The RTL is lint clean and passes its self-checking testbench against a reference model in simulation. It has not been run on an FPGA board or in silicon.

Interfaces

Port	Direction	Kind	Width	Notes
src	in	parallel	32

Standards

No external standard applies.

More in interrupt controllers

ID	Block	Maturity
of_plic	RISC-V PLIC	simulated
of_clic	RISC-V CLIC	planned
of_aplic	RISC-V APLIC	planned
of_imsic	RISC-V IMSIC	planned
of_gic_style	GIC-style interrupt distributor	planned