IP PortfolioSoC interconnectdebug_and_test
of_jtag_tdr
JTAG user test data register
Maturity simulatedTargets FPGA + ASICDifficulty EasyPriority 1
User-defined test data register with capture, shift and update stages attached to the OFIP JTAG TAP.
Simulated. The RTL is lint clean and passes its self-checking testbench against a reference model in simulation. It has not been run on an FPGA board or in silicon.
Interfaces
No external interfaces are defined for this entry yet.
Standards
- IEEE 1149.1-2013
More in debug_and_test
| ID | Block | Maturity |
|---|---|---|
| of_mbist_march | March C- memory BIST controller | simulated |
| of_wrap_1500 | IEEE 1500 core test wrapper | simulated |