IP PortfolioSoC interconnectdebug_and_test
of_mbist_march
March C- memory BIST controller
Maturity simulatedTargets FPGA + ASICDifficulty MediumPriority 1
Memory built-in self-test controller running March C- with optional checkerboard background and configurable read latency; its port matches the OFIP memory compiler BIST port.
Simulated. The RTL is lint clean and passes its self-checking testbench against a reference model in simulation. It has not been run on an FPGA board or in silicon.
Interfaces
No external interfaces are defined for this entry yet.
Standards
No external standard applies.
More in debug_and_test
| ID | Block | Maturity |
|---|---|---|
| of_wrap_1500 | IEEE 1500 core test wrapper | simulated |
| of_jtag_tdr | JTAG user test data register | simulated |