IP PortfolioSoC interconnectsystem management
of_pinmux
Pin multiplexer
Maturity simulatedTargets FPGA + ASICDifficulty EasyPriority 1
Configurable mapping of peripheral signals to pads with per-pad function select, pull, drive strength and input enable control.
Simulated. The RTL is lint clean and passes its self-checking testbench against a reference model in simulation. It has not been run on an FPGA board or in silicon.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | APB control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| periph_io | inout | parallel | 64 | |
| pad_ctrl | out | parallel | 256 |
Standards
No external standard applies.
Basis projects
Permissive open projects the implementation may build on.
- OpenTitan (Apache-2.0)
More in system management
| ID | Block | Maturity |
|---|---|---|
| of_bootrom_ctrl | Boot ROM and boot-mode controller | simulated |
| of_sysctrl | System controller | simulated |
| of_addr_remap | Address remap unit | planned |