Reset control unit

Maturity simulatedTargets FPGA + ASICDifficulty EasyPriority 1

Reset controller that sequences domain resets from power-on, watchdog, software and debug sources, records reset reason and provides per-block software resets.

Simulated. The RTL is lint clean and passes its self-checking testbench against a reference model in simulation. It has not been run on an FPGA board or in silicon.

Interfaces

Port	Direction	Kind	Width	Notes
ctrl	in/out	APB control bus	32	Control and status registers, including ID, VERSION and STATUS
rst_src	in	parallel	8
rst_out_n	out	parallel	16

Standards

No external standard applies.

More in clock, reset and power control

ID	Block	Maturity
of_clk_div	Integer clock divider (50 % duty)	fpga-routed
of_clk_gate	Clock-gating cell model (latch-based ICG)	simulated
of_clk_mux_gf	Glitch-free clock multiplexer	simulated
of_ccu	Clock control unit	simulated
of_ppu	Power policy unit	simulated
of_clk_mon	Clock monitor and frequency meter	planned
of_dvfs_ctrl	DVFS controller	planned