IP PortfolioSoC interconnectclock, reset and power control
of_clk_mux_gf
Glitch-free clock multiplexer
Maturity simulatedTargets FPGA + ASICDifficulty MediumPriority 1
2:1 clock multiplexer for asynchronous clocks with cross-coupled, synchronized enables (rising-edge synchronizer plus falling-edge enable flop per input) so that switching never produces a runt pulse; reports which input is active.
Simulated. The RTL is lint clean and passes its self-checking testbench against a reference model in simulation. It has not been run on an FPGA board or in silicon.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| clk_a | in | clock | 1 | |
| clk_b | in | clock | 1 | |
| clk_out | out | clock | 1 |
Standards
No external standard applies.
More in clock, reset and power control
| ID | Block | Maturity |
|---|---|---|
| of_clk_div | Integer clock divider (50 % duty) | fpga-routed |
| of_clk_gate | Clock-gating cell model (latch-based ICG) | simulated |
| of_ccu | Clock control unit | simulated |
| of_rcu | Reset control unit | simulated |
| of_ppu | Power policy unit | simulated |
| of_clk_mon | Clock monitor and frequency meter | planned |
| of_dvfs_ctrl | DVFS controller | planned |