IP PortfolioSoC interconnectclock domain crossing
of_sync_bus
Multi-bit bus synchronizer (handshake)
Maturity fpga-routedTargets FPGA + ASICDifficulty MediumPriority 1
Transfers WIDTH-bit words between asynchronous clock domains with valid/ready on both sides. The word is held in a source register while a four-phase handshake (of_sync_handshake) crosses, and is captured in the destination only after it has been stable for several destination cycles.
FPGA-routed. The block meets timing on a routed FPGA netlist at a stated clock and its testbench passes on that netlist. It has not yet run on a board or in silicon.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| s_in | in | valid-qualified bus | 32 | |
| m_out | out | valid-qualified bus | 32 | |
| src_clk | in | clock | 1 |
Standards
No external standard applies.
More in clock domain crossing
| ID | Block | Maturity |
|---|---|---|
| of_sync_bit | Multi-flop bit synchronizer | fpga-routed |
| of_sync_handshake | Four-phase req/ack handshake synchronizer | simulated |
| of_sync_pulse | Toggle pulse synchronizer | simulated |
| of_sync_reset | Reset synchronizer | simulated |