IP PortfolioSoC interconnectclock domain crossing
of_sync_reset
Reset synchronizer
Maturity simulatedTargets FPGA + ASICDifficulty EasyPriority 1
Asynchronous-assert, synchronous-deassert reset synchronizer with a 2-4 flop chain and a test-mode bypass, producing a clean active-low reset for one clock domain.
Simulated. The RTL is lint clean and passes its self-checking testbench against a reference model in simulation. It has not been run on an FPGA board or in silicon.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| rst_out_n | out | parallel | 1 |
Standards
No external standard applies.
More in clock domain crossing
| ID | Block | Maturity |
|---|---|---|
| of_sync_bit | Multi-flop bit synchronizer | fpga-routed |
| of_sync_bus | Multi-bit bus synchronizer (handshake) | fpga-routed |
| of_sync_handshake | Four-phase req/ack handshake synchronizer | simulated |
| of_sync_pulse | Toggle pulse synchronizer | simulated |