IP PortfolioVerification IPautomotive bus vip
of_vip_can_mon
CAN / CAN FD / CAN XL monitor and protocol checker
Maturity simulatedTargets FPGA + ASICDifficulty MediumPriority 1
CAN monitor decoding classical CAN, CAN FD and CAN XL frames with bit stuffing, CRC, ACK, error frames and bit timing checks at the configured sample point.
Simulated. The RTL is lint clean and passes its self-checking testbench against a reference model in simulation. It has not been run on an FPGA board or in silicon.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| tap | in | parallel | 2 | Observed interface signals |
| txn | out | AXI4-Stream | 128 | Decoded transactions for scoreboards |
Standards
- ISO 11898-1
- CiA 610-1
More in automotive bus vip
| ID | Block | Maturity |
|---|---|---|
| of_vip_can_bfm | CAN / CAN FD / CAN XL bus functional model and agent | simulated |
| of_vip_lin_mon | LIN monitor and protocol checker | planned |
| of_vip_lin_bfm | LIN bus functional model and agent | planned |
| of_vip_flexray_mon | FlexRay monitor and protocol checker | planned |
| of_vip_flexray_bfm | FlexRay bus functional model and agent | planned |