IP PortfolioVerification IPautomotive bus vip
of_vip_flexray_mon
FlexRay monitor and protocol checker
Maturity plannedTargets FPGA + ASICDifficulty HardPriority 3
FlexRay monitor decoding static and dynamic segment frames on both channels with header and frame CRC checks and cycle timing.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| tap | in | parallel | 4 | Observed interface signals |
| txn | out | AXI4-Stream | 128 | Decoded transactions for scoreboards |
Standards
- ISO 17458
More in automotive bus vip
| ID | Block | Maturity |
|---|---|---|
| of_vip_can_mon | CAN / CAN FD / CAN XL monitor and protocol checker | simulated |
| of_vip_can_bfm | CAN / CAN FD / CAN XL bus functional model and agent | simulated |
| of_vip_lin_mon | LIN monitor and protocol checker | planned |
| of_vip_lin_bfm | LIN bus functional model and agent | planned |
| of_vip_flexray_bfm | FlexRay bus functional model and agent | planned |