IP PortfolioVerification IPdisplay vip
of_vip_dp_mon
DisplayPort monitor and protocol checker
Maturity plannedTargets FPGA + ASICDifficulty HardPriority 3
DisplayPort monitor at the main-link symbol level decoding link training, main stream attributes, secondary data packets and AUX transactions.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| tap | in | parallel | 80 | Observed interface signals |
| txn | out | AXI4-Stream | 128 | Decoded transactions for scoreboards |
Standards
- VESA DisplayPort 2.1
More in display vip
| ID | Block | Maturity |
|---|---|---|
| of_vip_hdmi_mon | HDMI monitor and protocol checker | planned |
| of_vip_hdmi_bfm | HDMI bus functional model and agent | planned |
| of_vip_dp_bfm | DisplayPort bus functional model and agent | planned |