IP PortfolioVerification IPethernet vip
of_vip_eth_mii_mon
Ethernet MII/RMII/GMII/RGMII monitor and protocol checker
Maturity simulatedTargets FPGA + ASICDifficulty MediumPriority 1
Ethernet MAC-PHY interface monitor for MII, RMII, GMII and RGMII that extracts frames, checks preamble, SFD, FCS, inter-frame gap and RGMII DDR timing.
Simulated. The RTL is lint clean and passes its self-checking testbench against a reference model in simulation. It has not been run on an FPGA board or in silicon.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| tap | in | parallel | 14 | Observed interface signals |
| txn | out | AXI4-Stream | 128 | Decoded transactions for scoreboards |
Standards
- IEEE 802.3
Basis projects
Permissive open projects the implementation may build on.
- cocotbext-eth (MIT)
More in ethernet vip
| ID | Block | Maturity |
|---|---|---|
| of_vip_eth_mii_bfm | Ethernet MII/RMII/GMII/RGMII bus functional model and agent | simulated |
| of_vip_eth_xgmii_mon | Ethernet XGMII/XLGMII/CGMII monitor and protocol checker | planned |
| of_vip_eth_xgmii_bfm | Ethernet XGMII/XLGMII/CGMII bus functional model and agent | planned |
| of_vip_eth_pkt_gen | Ethernet packet generator and checker | planned |