IP PortfolioVerification IPverification infrastructure
of_vip_formal_props
Bus protocol formal property sets
Maturity simulatedTargets FPGA + ASICDifficulty MediumPriority 1
Assume/assert property sets for AXI4, AXI4-Lite, AXI4-Stream, APB, AHB and Wishbone, for proving bus compliance of OFIP blocks with formal tools.
Simulated. The RTL is lint clean and passes its self-checking testbench against a reference model in simulation. It has not been run on an FPGA board or in silicon.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| tap | in | parallel | 512 |
Standards
- IEEE 1800-2017
- AMBA AXI4
- Wishbone B4
More in verification infrastructure
| ID | Block | Maturity |
|---|---|---|
| of_vip_scoreboard | Transaction scoreboard | simulated |
| of_vip_coverage | Functional coverage collector | simulated |
| of_vip_mem_model | Sparse memory model | simulated |
| of_vip_clk_rst_gen | Clock and reset generator | simulated |
| of_vip_ral_gen | Register model generator | simulated |
| of_vip_irq_mon | Interrupt monitor | planned |
| of_vip_gpio_agent | GPIO pin agent | planned |
| of_vip_stream_tg | Stream traffic generator and checker | simulated |
| of_vip_cdc_assert | CDC and reset assertion library | planned |
| of_vip_power_aware | Power-aware checker | planned |