IP PortfolioVerification IPverification infrastructure
of_vip_mem_model
Sparse memory model
Maturity simulatedTargets FPGA + ASICDifficulty EasyPriority 1
Sparse associative memory model with backdoor load and dump, byte-enable writes, uninitialized-read detection and configurable latency, shared by bus agents.
Simulated. The RTL is lint clean and passes its self-checking testbench against a reference model in simulation. It has not been run on an FPGA board or in silicon.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| s_mem | in | valid-qualified bus | 128 | |
| rdata | out | valid-qualified bus | 128 |
Standards
No external standard applies.
Basis projects
Permissive open projects the implementation may build on.
- cocotbext-axi (MIT)
More in verification infrastructure
| ID | Block | Maturity |
|---|---|---|
| of_vip_scoreboard | Transaction scoreboard | simulated |
| of_vip_coverage | Functional coverage collector | simulated |
| of_vip_clk_rst_gen | Clock and reset generator | simulated |
| of_vip_ral_gen | Register model generator | simulated |
| of_vip_irq_mon | Interrupt monitor | planned |
| of_vip_gpio_agent | GPIO pin agent | planned |
| of_vip_stream_tg | Stream traffic generator and checker | simulated |
| of_vip_cdc_assert | CDC and reset assertion library | planned |
| of_vip_power_aware | Power-aware checker | planned |
| of_vip_formal_props | Bus protocol formal property sets | simulated |