IP PortfolioVerification IPverification infrastructure
of_vip_ref_model_bridge
Reference model bridge
Maturity plannedTargets FPGA + ASICDifficulty EasyPriority 2
DPI-C and cocotb bridge that runs C, C++ or Python reference models in lockstep with the DUT and feeds results to scoreboards.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| s_txn | in | AXI4-Stream | 128 | |
| txn | out | AXI4-Stream | 128 | Decoded transactions for scoreboards |
Standards
- IEEE 1800-2017
Basis projects
Permissive open projects the implementation may build on.
- cocotb (BSD-3-Clause)
More in verification infrastructure
| ID | Block | Maturity |
|---|---|---|
| of_vip_scoreboard | Transaction scoreboard | simulated |
| of_vip_coverage | Functional coverage collector | simulated |
| of_vip_mem_model | Sparse memory model | simulated |
| of_vip_clk_rst_gen | Clock and reset generator | simulated |
| of_vip_ral_gen | Register model generator | simulated |
| of_vip_irq_mon | Interrupt monitor | planned |
| of_vip_gpio_agent | GPIO pin agent | planned |
| of_vip_stream_tg | Stream traffic generator and checker | simulated |
| of_vip_cdc_assert | CDC and reset assertion library | planned |
| of_vip_power_aware | Power-aware checker | planned |