IP PortfolioDatapath and DSPstorage helpers
of_ram_wrap
Generic RAM wrapper
Maturity simulatedTargets FPGA + ASICDifficulty EasyPriority 1
Technology-independent single-port, simple dual-port and true dual-port RAM wrapper with byte enables, optional SECDED, output registers and behavioral model; maps to FPGA block RAM or ASIC SRAM macros.
Simulated. The RTL is lint clean and passes its self-checking testbench against a reference model in simulation. It has not been run on an FPGA board or in silicon.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| port_a | in | valid-qualified bus | 64 | |
| rdata | out | parallel | 64 |
Standards
No external standard applies.
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