IP PortfolioInterface PHYsusb_phy
of_typec_combo_phy
USB-C combo PHY (USB 3.2 + DisplayPort)
Maturity plannedTargets ASIC (CMOS) onlyDifficulty Very hardPriority 2
Type-C combo PHY with orientation flip mux and four lanes shareable between USB 3.2 and DisplayPort alternate mode, with AUX channel.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | APB control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| lane | inout | differential pair | 4 | |
| aux | inout | differential pair | 1 | |
| usb_pipe | inout | parallel | 32 | |
| dp_tx | in | parallel | 160 | |
| refclk | in | differential pair | 1 |
Standards
- USB 3.2
- VESA DisplayPort 1.4a
- USB Type-C Cable and Connector Specification 2.4
More in usb_phy
| ID | Block | Maturity |
|---|---|---|
| of_usb_fs_xcvr | USB full-speed transceiver | planned |
| of_usb2_phy | USB 2.0 PHY (UTMI+) | planned |
| of_eusb2_phy | eUSB2 PHY | planned |
| of_usb3_phy | USB 3.2 PHY | planned |
| of_usb4_phy | USB4 PHY | planned |