IP PortfolioInterface PHYsusb_phy
of_eusb2_phy
eUSB2 PHY
Maturity plannedTargets ASIC (CMOS) onlyDifficulty HardPriority 3
Embedded USB2 PHY using 1 V class signalling for advanced nodes without 3.3 V I/O, with UTMI+ interface and native or repeater modes.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | APB control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| edp | inout | analog | 1 | |
| edm | inout | analog | 1 | |
| utmi_tx | in | parallel | 10 | |
| utmi_rx | out | parallel | 12 | |
| refclk | in | clock | 1 |
Standards
- eUSB2 Physical Layer Supplement to USB 2.0
More in usb_phy
| ID | Block | Maturity |
|---|---|---|
| of_usb_fs_xcvr | USB full-speed transceiver | planned |
| of_usb2_phy | USB 2.0 PHY (UTMI+) | planned |
| of_usb3_phy | USB 3.2 PHY | planned |
| of_usb4_phy | USB4 PHY | planned |
| of_typec_combo_phy | USB-C combo PHY (USB 3.2 + DisplayPort) | planned |