IP PortfolioInterface PHYsusb_phy
of_usb3_phy
USB 3.2 PHY
Maturity plannedTargets ASIC (CMOS) onlyDifficulty HardPriority 2
USB 3.2 Gen 1/Gen 2 PHY at 5 and 10 Gb/s with PIPE interface, LFPS, SSC and receiver equalisation, paired with a USB 2.0 PHY.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | APB control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| tx | out | differential pair | 1 | |
| rx | in | differential pair | 1 | |
| refclk | in | differential pair | 1 | |
| pma_tx | in | parallel | 32 | |
| pma_rx | out | parallel | 32 |
Standards
- USB 3.2
- Intel PIPE 5.1
More in usb_phy
| ID | Block | Maturity |
|---|---|---|
| of_usb_fs_xcvr | USB full-speed transceiver | planned |
| of_usb2_phy | USB 2.0 PHY (UTMI+) | planned |
| of_eusb2_phy | eUSB2 PHY | planned |
| of_usb4_phy | USB4 PHY | planned |
| of_typec_combo_phy | USB-C combo PHY (USB 3.2 + DisplayPort) | planned |