IP PortfolioInterface PHYsmemory_phy
of_xspi_phy
xSPI / Octal DDR PHY
Maturity plannedTargets ASIC (CMOS) onlyDifficulty HardPriority 2
Octal SPI and HyperBus pad PHY with master DLL, DQS or RWDS-based read capture and per-bit delay lines for 200 MHz DTR operation.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | APB control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| io | inout | parallel | 8 | |
| dqs | inout | serial | 1 | |
| sclk | out | differential pair | 1 | |
| core_io | inout | parallel | 16 |
Standards
- JEDEC JESD251
More in memory_phy
| ID | Block | Maturity |
|---|---|---|
| of_ddr4_phy | DDR3/DDR4 PHY | planned |
| of_ddr5_phy | DDR5 PHY | planned |
| of_lpddr4_phy | LPDDR4/LPDDR4X PHY | planned |
| of_lpddr5_phy | LPDDR5/LPDDR5X PHY | planned |
| of_lpddr6_phy | LPDDR6 PHY | planned |
| of_gddr6_phy | GDDR6 PHY | planned |
| of_gddr7_phy | GDDR7 PHY | planned |
| of_hbm2e_phy | HBM2E PHY | planned |
| of_hbm3_phy | HBM3/HBM3E PHY | planned |
| of_hbm4_phy | HBM4 PHY | planned |