IP PortfolioProcessorsinterrupt
of_cpu_aclint
Core-local interruptor (ACLINT)
Maturity simulatedTargets FPGA + ASICDifficulty EasyPriority 1
Machine timer, machine software interrupt and supervisor software interrupt devices for multi-hart systems.
Simulated. The RTL is lint clean and passes its self-checking testbench against a reference model in simulation. It has not been run on an FPGA board or in silicon.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | AXI4-Lite control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| mtip | out | parallel | 8 | |
| msip | out | parallel | 8 |
Standards
- RISC-V ACLINT 1.0 (draft)
More in interrupt
| ID | Block | Maturity |
|---|---|---|
| of_cpu_plic | Platform-level interrupt controller | simulated |
| of_cpu_clic | Core-local interrupt controller (CLIC) | simulated |
| of_cpu_aia | Advanced interrupt architecture (APLIC and IMSIC) | planned |
| of_cpu_mailbox | Inter-processor mailbox and semaphores | planned |