IP PortfolioProcessorsinterrupt
of_cpu_plic
Platform-level interrupt controller
Maturity simulatedTargets FPGA + ASICDifficulty EasyPriority 1
PLIC with up to 1023 sources, configurable priorities and thresholds and per-hart context claim and complete.
Simulated. The RTL is lint clean and passes its self-checking testbench against a reference model in simulation. It has not been run on an FPGA board or in silicon.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | AXI4-Lite control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| src | in | parallel | 256 | |
| ctx_irq | out | parallel | 16 |
Standards
- RISC-V PLIC 1.0.0
More in interrupt
| ID | Block | Maturity |
|---|---|---|
| of_cpu_aclint | Core-local interruptor (ACLINT) | simulated |
| of_cpu_clic | Core-local interrupt controller (CLIC) | simulated |
| of_cpu_aia | Advanced interrupt architecture (APLIC and IMSIC) | planned |
| of_cpu_mailbox | Inter-processor mailbox and semaphores | planned |