IP PortfolioProcessorsinterrupt
of_cpu_clic
Core-local interrupt controller (CLIC)
Maturity simulatedTargets FPGA + ASICDifficulty MediumPriority 1
Per-hart interrupt controller with level and priority per source, selective hardware vectoring and preemption.
Simulated. The RTL is lint clean and passes its self-checking testbench against a reference model in simulation. It has not been run on an FPGA board or in silicon.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | APB control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| src | in | parallel | 256 | |
| irq_req | out | valid-qualified bus | 12 |
Standards
- RISC-V CLIC (draft)
More in interrupt
| ID | Block | Maturity |
|---|---|---|
| of_cpu_plic | Platform-level interrupt controller | simulated |
| of_cpu_aclint | Core-local interruptor (ACLINT) | simulated |
| of_cpu_aia | Advanced interrupt architecture (APLIC and IMSIC) | planned |
| of_cpu_mailbox | Inter-processor mailbox and semaphores | planned |