of_cpu_cluster_coherent

Coherent RV64 multicore cluster

Maturity plannedTargets FPGA + ASICDifficulty Very hardPriority 1

One to eight RV64 cores with private L1, shared L2, a snoop filter or directory for coherence and a single coherent system port.

Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.

Interfaces

Port	Direction	Kind	Width	Notes
ctrl	in/out	AXI4-Lite control bus	32	Control and status registers, including ID, VERSION and STATUS
irq	out	interrupt	1	Interrupt request
ext_irq	in	parallel	32

Standards

RISC-V RV64GC
RISC-V Ztso
AMBA CHI
TileLink

More in riscv_cluster

ID	Block	Maturity
of_cpu_cluster_tcdm	Shared-memory RV32 compute cluster	planned
of_cpu_manycore_tile	Many-core mesh tile	planned
of_cpu_acp	Accelerator coherency port	planned