IP PortfolioProcessorsriscv_cluster
of_cpu_manycore_tile
Many-core mesh tile
Maturity plannedTargets FPGA + ASICDifficulty Very hardPriority 3
Replicable tile with an RV64 core, L1 caches, an L2 slice and a mesh NoC router for building 16 to 256 core arrays.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| noc_n | inout | parallel | 128 | |
| noc_e | inout | parallel | 128 |
Standards
- RISC-V RV64GC
More in riscv_cluster
| ID | Block | Maturity |
|---|---|---|
| of_cpu_cluster_coherent | Coherent RV64 multicore cluster | planned |
| of_cpu_cluster_tcdm | Shared-memory RV32 compute cluster | planned |
| of_cpu_acp | Accelerator coherency port | planned |