of_cpu_cluster_tcdm

Shared-memory RV32 compute cluster

Maturity plannedTargets FPGA + ASICDifficulty HardPriority 2

Cluster of RV32 cores sharing a multi-banked tightly coupled data memory through a single-cycle interconnect, with a cluster DMA and event unit for parallel DSP.

Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.

Interfaces

Port	Direction	Kind	Width	Notes
ctrl	in/out	AXI4-Lite control bus	32	Control and status registers, including ID, VERSION and STATUS
irq	out	interrupt	1	Interrupt request
evt_in	in	parallel	16

Standards

RISC-V RV32IMFC

More in riscv_cluster

ID	Block	Maturity
of_cpu_cluster_coherent	Coherent RV64 multicore cluster	planned
of_cpu_manycore_tile	Many-core mesh tile	planned
of_cpu_acp	Accelerator coherency port	planned