IP PortfolioProcessorsfpga_soft
of_cpu_fpga_soft_mcu
FPGA soft microcontroller SoC
Maturity plannedTargets FPGA + ASICDifficulty MediumPriority 2
Complete soft microcontroller for FPGAs with RV32 core, memories, peripherals, on-chip debugger and bootloader.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | Wishbone control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| gpio | inout | parallel | 32 |
Standards
- RISC-V RV32IMC
- RISC-V Debug 0.13
Basis projects
Permissive open projects the implementation may build on.
- NEORV32 (BSD-3-Clause)
More in fpga_soft
| ID | Block | Maturity |
|---|---|---|
| of_cpu_fpga_soft_rv32 | Configurable FPGA soft RV32 core | simulated |
| of_cpu_fpga_soft_tiny | Size-optimised FPGA soft core | planned |
| of_cpu_fpga_soft_linux | FPGA Linux-capable soft SoC | planned |