of_cpu_fpga_soft_rv32

Configurable FPGA soft RV32 core

Maturity simulatedTargets FPGA + ASICDifficulty MediumPriority 1

Pipeline-configurable RV32IM(A)(C) soft core tuned for FPGA LUT and DSP resources with optional caches and MMU.

Simulated. The RTL is lint clean and passes its self-checking testbench against a reference model in simulation. It has not been run on an FPGA board or in silicon.

Interfaces

Port	Direction	Kind	Width	Notes
ext_irq	in	parallel	32

Standards

RISC-V RV32IMAC
RISC-V Debug 0.13

Basis projects

Permissive open projects the implementation may build on.

VexRiscv (SpinalHDL) (MIT)

Notes

Instruction and data memory ports (AXI4, AHB or OBI) are master interfaces and are added when the skeleton is promoted; the catalog lists only interrupt and debug pins.

More in fpga_soft

ID	Block	Maturity
of_cpu_fpga_soft_tiny	Size-optimised FPGA soft core	planned
of_cpu_fpga_soft_mcu	FPGA soft microcontroller SoC	planned
of_cpu_fpga_soft_linux	FPGA Linux-capable soft SoC	planned