IP PortfolioProcessorsfpga_soft
of_cpu_fpga_soft_tiny
Size-optimised FPGA soft core
Maturity plannedTargets FPGA + ASICDifficulty EasyPriority 2
Multi-cycle RV32I/E soft core with a native memory interface that fits in a few hundred LUTs for control-plane FPGA designs.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ext_irq | in | parallel | 32 |
Standards
- RISC-V RV32IMC
Basis projects
Permissive open projects the implementation may build on.
- PicoRV32 (ISC)
Notes
Instruction and data memory ports (AXI4, AHB or OBI) are master interfaces and are added when the skeleton is promoted; the catalog lists only interrupt and debug pins.
More in fpga_soft
| ID | Block | Maturity |
|---|---|---|
| of_cpu_fpga_soft_rv32 | Configurable FPGA soft RV32 core | simulated |
| of_cpu_fpga_soft_mcu | FPGA soft microcontroller SoC | planned |
| of_cpu_fpga_soft_linux | FPGA Linux-capable soft SoC | planned |