IP PortfolioProcessorsmcu_subsystem
of_cpu_mcu_subsys_basic
Basic RV32 microcontroller subsystem
Maturity simulatedTargets FPGA + ASICDifficulty MediumPriority 1
RV32IMC core with SRAM, boot ROM, UART, SPI, I2C, GPIO, timers and a debug port on an AHB/APB fabric.
Simulated. The RTL is lint clean and passes its self-checking testbench against a reference model in simulation. It has not been run on an FPGA board or in silicon.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| gpio | inout | parallel | 32 | |
| uart_tx | out | serial | 1 | |
| uart_rx | in | serial | 1 |
Standards
- RISC-V RV32IMC
- RISC-V Debug 0.13
- AMBA AHB-Lite
- AMBA APB
More in mcu_subsystem
| ID | Block | Maturity |
|---|---|---|
| of_cpu_mcu_subsys_lowpower | Low-power IoT MCU subsystem | planned |
| of_cpu_mcu_subsys_auto | Automotive MCU subsystem | planned |
| of_cpu_soc_mgmt | SoC management controller | simulated |
| of_cpu_power_ctrl | Core power and clock controller | planned |
| of_cpu_hw_rtos | Hardware RTOS scheduler | planned |
| of_cpu_pio | Programmable I/O state machines | planned |
| of_cpu_microsequencer | Programmable microsequencer | planned |
| of_cpu_amo_unit | Far atomic memory operation unit | planned |
| of_cpu_boot_ctrl | Multi-source boot controller | planned |