IP PortfolioProcessorsmcu_subsystem
of_cpu_mcu_subsys_lowpower
Low-power IoT MCU subsystem
Maturity plannedTargets FPGA + ASICDifficulty HardPriority 2
Microcontroller subsystem with an always-on domain, RTC, retention SRAM, wake-up controller and power-gated main core domain.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| wake_src | in | parallel | 8 | |
| pwr_ctrl | out | parallel | 8 |
Standards
- RISC-V RV32IMC
More in mcu_subsystem
| ID | Block | Maturity |
|---|---|---|
| of_cpu_mcu_subsys_basic | Basic RV32 microcontroller subsystem | simulated |
| of_cpu_mcu_subsys_auto | Automotive MCU subsystem | planned |
| of_cpu_soc_mgmt | SoC management controller | simulated |
| of_cpu_power_ctrl | Core power and clock controller | planned |
| of_cpu_hw_rtos | Hardware RTOS scheduler | planned |
| of_cpu_pio | Programmable I/O state machines | planned |
| of_cpu_microsequencer | Programmable microsequencer | planned |
| of_cpu_amo_unit | Far atomic memory operation unit | planned |
| of_cpu_boot_ctrl | Multi-source boot controller | planned |