IP PortfolioProcessorsmcu_subsystem
of_cpu_power_ctrl
Core power and clock controller
Maturity plannedTargets FPGA + ASICDifficulty MediumPriority 2
Per-core clock gating, power-gating and state retention sequencing driven by WFI and software requests, with isolation control.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | APB control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
| pwr_sw | out | parallel | 8 | |
| iso_en | out | parallel | 8 |
Standards
No external standard applies.
More in mcu_subsystem
| ID | Block | Maturity |
|---|---|---|
| of_cpu_mcu_subsys_basic | Basic RV32 microcontroller subsystem | simulated |
| of_cpu_mcu_subsys_lowpower | Low-power IoT MCU subsystem | planned |
| of_cpu_mcu_subsys_auto | Automotive MCU subsystem | planned |
| of_cpu_soc_mgmt | SoC management controller | simulated |
| of_cpu_hw_rtos | Hardware RTOS scheduler | planned |
| of_cpu_pio | Programmable I/O state machines | planned |
| of_cpu_microsequencer | Programmable microsequencer | planned |
| of_cpu_amo_unit | Far atomic memory operation unit | planned |
| of_cpu_boot_ctrl | Multi-source boot controller | planned |