IP PortfolioQuantum controltiming
of_q_clock_sync
Multi-board clock synchronisation
Maturity plannedTargets FPGA + ASICDifficulty HardPriority 1
Sub-nanosecond clock and time synchronisation across chassis using precision time protocol with phase measurement and DDMTD tracking.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | AXI4-Lite control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
| ref_clk | in | clock | 1 | |
| sync_clk | out | clock | 1 |
Standards
- IEEE 1588-2019
More in timing
| ID | Block | Maturity |
|---|---|---|
| of_q_tdc | Picosecond time-to-digital converter | planned |
| of_q_trigger_dist | Deterministic trigger distribution | planned |