IP PortfolioQuantum controltiming
of_q_trigger_dist
Deterministic trigger distribution
Maturity plannedTargets FPGA + ASICDifficulty HardPriority 1
Fixed-latency trigger and timestamp distribution over serial links with latency measurement and compensation across many control boards.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | APB control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
| link_tx | out | differential pair | 1 | |
| link_rx | in | differential pair | 1 | |
| trig_out | out | parallel | 8 |
Standards
No external standard applies.
More in timing
| ID | Block | Maturity |
|---|---|---|
| of_q_tdc | Picosecond time-to-digital converter | planned |
| of_q_clock_sync | Multi-board clock synchronisation | planned |