IP PortfolioQuantum controltiming
of_q_tdc
Picosecond time-to-digital converter
Maturity plannedTargets ASIC (CMOS) onlyDifficulty HardPriority 1
Tapped delay line or Vernier TDC with bin calibration and sub-10 ps resolution target for photon timing and trigger alignment.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | APB control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
| hit_in | in | parallel | 8 | |
| ts_out | out | valid-qualified bus | 48 |
Standards
No external standard applies.
More in timing
| ID | Block | Maturity |
|---|---|---|
| of_q_trigger_dist | Deterministic trigger distribution | planned |
| of_q_clock_sync | Multi-board clock synchronisation | planned |