IP PortfolioQuantum controlcontrol_plane
of_q_control_processor
QPU control processor
Maturity plannedTargets FPGA + ASICDifficulty Very hardPriority 1
Real-time processor with a quantum instruction set extension that issues timed operations, handles measurement results and runs classical control flow.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | AXI4-Lite control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
Standards
- OpenQASM 3.0
More in control_plane
| ID | Block | Maturity |
|---|---|---|
| of_q_pulse_queue | Timed pulse instruction queue | simulated |
| of_q_host_if | Control plane host interface | simulated |
| of_q_shot_accumulator | Shot accumulator and histogrammer | simulated |
| of_q_variational_loop | Near-time variational optimiser | planned |
| of_q_entanglement_link | Inter-QPU entanglement link controller | planned |