IP PortfolioQuantum controlcontrol_plane
of_q_entanglement_link
Inter-QPU entanglement link controller
Maturity plannedTargets FPGA + ASICDifficulty HardPriority 3
Timing and heralding controller for remote entanglement attempts between modules, tracking success signals and retry schedules.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | AXI4-Lite control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
| herald_in | in | parallel | 8 | |
| attempt_out | out | parallel | 8 |
Standards
No external standard applies.
More in control_plane
| ID | Block | Maturity |
|---|---|---|
| of_q_control_processor | QPU control processor | planned |
| of_q_pulse_queue | Timed pulse instruction queue | simulated |
| of_q_host_if | Control plane host interface | simulated |
| of_q_shot_accumulator | Shot accumulator and histogrammer | simulated |
| of_q_variational_loop | Near-time variational optimiser | planned |