IP PortfolioQuantum controlcontrol_plane
of_q_host_if
Control plane host interface
Maturity simulatedTargets FPGA + ASICDifficulty MediumPriority 1
Job queue, program and waveform upload, result streaming and status interface between host servers and the control system over PCIe or Ethernet DMA.
Simulated. The RTL is lint clean and passes its self-checking testbench against a reference model in simulation. It has not been run on an FPGA board or in silicon.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | AXI4-Lite control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
| res_out | out | AXI4-Stream | 256 |
Standards
No external standard applies.
More in control_plane
| ID | Block | Maturity |
|---|---|---|
| of_q_control_processor | QPU control processor | planned |
| of_q_pulse_queue | Timed pulse instruction queue | simulated |
| of_q_shot_accumulator | Shot accumulator and histogrammer | simulated |
| of_q_variational_loop | Near-time variational optimiser | planned |
| of_q_entanglement_link | Inter-QPU entanglement link controller | planned |