IP PortfolioQuantum controlspin_qubit
of_q_gate_dac_seq
Gate voltage DAC sequencer
Maturity simulatedTargets FPGA + ASICDifficulty MediumPriority 1
Sequencer for many gate electrode DACs with virtual gate matrix transformation, ramps and pulse segments for quantum dot control.
Simulated. The RTL is lint clean and passes its self-checking testbench against a reference model in simulation. It has not been run on an FPGA board or in silicon.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | AXI4-Lite control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
| dac_codes | out | valid-qualified bus | 1024 |
Standards
No external standard applies.
More in spin_qubit
| ID | Block | Maturity |
|---|---|---|
| of_q_rf_reflectometry | RF reflectometry readout | simulated |
| of_q_charge_sensor_lock | Charge sensor operating point feedback | planned |
| of_q_spin_shuttle | Spin conveyor shuttling generator | planned |