of_q_rf_reflectometry

RF reflectometry readout

Maturity simulatedTargets FPGA + ASICDifficulty MediumPriority 1

Demodulation and integration of RF reflectometry signals from charge sensors or gate sensors with thresholding into spin states.

Simulated. The RTL is lint clean and passes its self-checking testbench against a reference model in simulation. It has not been run on an FPGA board or in silicon.

Interfaces

Port	Direction	Kind	Width	Notes
ctrl	in/out	AXI4-Lite control bus	32	Control and status registers, including ID, VERSION and STATUS
irq	out	interrupt	1	Interrupt request
adc_in	in	AXI4-Stream	256
state_out	out	valid-qualified bus	16

Standards

No external standard applies.

More in spin_qubit

ID	Block	Maturity
of_q_gate_dac_seq	Gate voltage DAC sequencer	simulated
of_q_charge_sensor_lock	Charge sensor operating point feedback	planned
of_q_spin_shuttle	Spin conveyor shuttling generator	planned