IP PortfolioQuantum controlspin_qubit
of_q_spin_shuttle
Spin conveyor shuttling generator
Maturity plannedTargets FPGA + ASICDifficulty MediumPriority 3
Multi-phase phase-locked sine generator for conveyor-mode electron shuttling between spin qubit registers.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | APB control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
| phase_out | out | valid-qualified bus | 64 |
Standards
No external standard applies.
More in spin_qubit
| ID | Block | Maturity |
|---|---|---|
| of_q_gate_dac_seq | Gate voltage DAC sequencer | simulated |
| of_q_rf_reflectometry | RF reflectometry readout | simulated |
| of_q_charge_sensor_lock | Charge sensor operating point feedback | planned |