IP PortfolioSensing and RFwireless_baseband
of_wl_dvbs2x_demod
DVB-S2X demodulator
Maturity plannedTargets FPGA + ASICDifficulty Very hardPriority 2
Symbol timing and carrier recovery, PL header decoding and APSK demapping with soft outputs for satellite broadband.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | AXI4-Lite control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
| iq_in | in | AXI4-Stream | 32 | |
| llr | out | AXI4-Stream | 64 |
Standards
- ETSI EN 302 307-2
More in wireless_baseband
| ID | Block | Maturity |
|---|---|---|
| of_wl_nr_ofdm_mod | 5G NR OFDM modulator | planned |
| of_wl_nr_ofdm_demod | 5G NR OFDM demodulator | planned |
| of_wl_nr_chest | 5G NR channel estimator | planned |
| of_wl_mimo_detector | MIMO detector | planned |
| of_wl_nr_beam_mgmt | 5G NR beam management engine | planned |
| of_wl_nr_prach | 5G NR PRACH detector | planned |
| of_wl_nr_precoder | 5G NR layer mapper and precoder | planned |
| of_wl_lte_phy | LTE PHY baseband | planned |
| of_wl_nbiot_phy | NB-IoT and LTE-M PHY | planned |
| of_wl_wifi6_bb | Wi-Fi 6 baseband | planned |