IP PortfolioSoC interconnectmonitoring and error reporting
of_bus_timeout
Bus transaction timeout monitor
Maturity plannedTargets FPGA + ASICDifficulty MediumPriority 2
Watches outstanding transactions on an AXI4 or APB path, completes hung transactions with an error response after a programmable timeout and logs the address.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | APB control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| irq | out | interrupt | 1 | Interrupt request |
| s_axi | in | valid-qualified bus | 256 | AXI4 slave port (AW/W/AR channels) |
| m_axi | out | valid-qualified bus | 256 | AXI4 master port (AW/W/AR channels) |
Standards
- AMBA AXI4
- AMBA APB4
More in monitoring and error reporting
| ID | Block | Maturity |
|---|---|---|
| of_axi_perfmon | AXI4 performance monitor | planned |
| of_hpm_counters | Hardware event counter bank | planned |
| of_ras_reri | RAS error record unit (RERI) | planned |