IP PortfolioSoC interconnectnetwork on chip
of_noc_gen
NoC topology generator
Maturity plannedTargets FPGA + ASICDifficulty Very hardPriority 2
Generator that assembles routers, network interfaces, links and clock-domain crossings into mesh, torus, ring or custom topologies from a topology description, with deadlock-free routing tables.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| ctrl | in/out | APB control bus | 32 | Control and status registers, including ID, VERSION and STATUS |
| ni_ports | inout | parallel | 512 |
Standards
No external standard applies.
More in network on chip
| ID | Block | Maturity |
|---|---|---|
| of_noc_router | NoC router | simulated |
| of_noc_ni_axi | AXI4 NoC network interface | simulated |
| of_noc_link_cdc | NoC link pipeline and clock crossing | planned |