IP PortfolioSoC interconnectnetwork on chip
of_noc_ni_axi
AXI4 NoC network interface
Maturity simulatedTargets FPGA + ASICDifficulty HardPriority 1
Network interface that packetizes AXI4 transactions into NoC flits and back, with ID tables, per-ID ordering and address-to-node mapping (reorder buffers are planned, not implemented).
Simulated. The RTL is lint clean and passes its self-checking testbench against a reference model in simulation. It has not been run on an FPGA board or in silicon.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| s_axi | in | valid-qualified bus | 256 | AXI4 slave port (AW/W/AR channels) |
| flit_out | out | valid-qualified bus | 128 | |
| flit_in | in | valid-qualified bus | 128 |
Standards
- AMBA AXI4
More in network on chip
| ID | Block | Maturity |
|---|---|---|
| of_noc_router | NoC router | simulated |
| of_noc_gen | NoC topology generator | planned |
| of_noc_link_cdc | NoC link pipeline and clock crossing | planned |