IP PortfolioSoC interconnectnetwork on chip
of_noc_router
NoC router
Maturity simulatedTargets FPGA + ASICDifficulty HardPriority 1
Packet-switched wormhole router with virtual channels, credit-based flow control, XY routing and separable allocators (implemented as a 5-port mesh router; configurable port count and table-based routing are planned).
Simulated. The RTL is lint clean and passes its self-checking testbench against a reference model in simulation. It has not been run on an FPGA board or in silicon.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| in_ports | in | valid-qualified bus | 256 | |
| out_ports | out | valid-qualified bus | 256 |
Standards
No external standard applies.
More in network on chip
| ID | Block | Maturity |
|---|---|---|
| of_noc_ni_axi | AXI4 NoC network interface | simulated |
| of_noc_gen | NoC topology generator | planned |
| of_noc_link_cdc | NoC link pipeline and clock crossing | planned |