IP PortfolioSoC interconnectwishbone, tilelink and obi
of_wb_axil_bridge
Wishbone and AXI4-Lite bridges
Maturity plannedTargets FPGA + ASICDifficulty EasyPriority 2
Bridges in both directions between Wishbone B4 (classic and pipelined) and AXI4-Lite, with error mapping and byte-select conversion.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| s_port | in | valid-qualified bus | 128 | |
| m_port | out | valid-qualified bus | 128 |
Standards
- Wishbone B4
- AMBA AXI4-Lite
More in wishbone, tilelink and obi
| ID | Block | Maturity |
|---|---|---|
| of_wb_ic | Wishbone B4 shared-bus interconnect | simulated |
| of_wb_xbar | Wishbone B4 pipelined crossbar | planned |
| of_tlul_xbar | TileLink TL-UL crossbar | planned |
| of_tl_axi4_bridge | TileLink to AXI4 bridge | planned |
| of_obi_xbar | OBI crossbar and AXI4 bridge | planned |