IP PortfolioSoC interconnectwishbone, tilelink and obi
of_obi_xbar
OBI crossbar and AXI4 bridge
Maturity plannedTargets FPGA + ASICDifficulty MediumPriority 2
Open Bus Interface crossbar for OBI-based RISC-V cores, with an OBI to AXI4 (and AXI4-Lite) bridge for connection to AMBA fabrics.
Planned. This block is specified in the catalog with its interfaces and targets. No implementation exists yet; the skeleton command below generates a lint-clean shell with its ports and registers.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| s_obi | in | valid-qualified bus | 72 | |
| m_obi | out | valid-qualified bus | 72 |
Standards
- OpenHW Group OBI 1.6
- AMBA AXI4
More in wishbone, tilelink and obi
| ID | Block | Maturity |
|---|---|---|
| of_wb_ic | Wishbone B4 shared-bus interconnect | simulated |
| of_wb_xbar | Wishbone B4 pipelined crossbar | planned |
| of_wb_axil_bridge | Wishbone and AXI4-Lite bridges | planned |
| of_tlul_xbar | TileLink TL-UL crossbar | planned |
| of_tl_axi4_bridge | TileLink to AXI4 bridge | planned |