IP PortfolioSoC interconnectwishbone, tilelink and obi
of_wb_ic
Wishbone B4 shared-bus interconnect
Maturity simulatedTargets FPGA + ASICDifficulty MediumPriority 1
Wishbone B4 classic shared-bus interconnect for N masters and M slaves with round-robin bus arbitration (owner keeps the bus for the whole cycle), base/mask address decoding and an error response for unmapped addresses.
Simulated. The RTL is lint clean and passes its self-checking testbench against a reference model in simulation. It has not been run on an FPGA board or in silicon.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| s_wb | in | valid-qualified bus | 72 | |
| m_wb | out | valid-qualified bus | 72 |
Standards
- Wishbone B4
More in wishbone, tilelink and obi
| ID | Block | Maturity |
|---|---|---|
| of_wb_xbar | Wishbone B4 pipelined crossbar | planned |
| of_wb_axil_bridge | Wishbone and AXI4-Lite bridges | planned |
| of_tlul_xbar | TileLink TL-UL crossbar | planned |
| of_tl_axi4_bridge | TileLink to AXI4 bridge | planned |
| of_obi_xbar | OBI crossbar and AXI4 bridge | planned |