IP PortfolioVerification IPdebug interface vip
of_vip_jtag_bfm
JTAG bus functional model and agent
Maturity simulatedTargets FPGA + ASICDifficulty EasyPriority 1
JTAG host agent issuing IR/DR scans, IDCODE checks and boundary-scan tests, with RISC-V DTM and IEEE 1687 access sequences.
Simulated. The RTL is lint clean and passes its self-checking testbench against a reference model in simulation. It has not been run on an FPGA board or in silicon.
Interfaces
| Port | Direction | Kind | Width | Notes |
|---|---|---|---|---|
| tck | out | clock | 1 | |
| tms | out | serial | 1 | |
| tdi | out | serial | 1 | |
| tdo | in | serial | 1 | |
| trst_n | out | serial | 1 |
Standards
- IEEE 1149.1
- IEEE 1149.6
More in debug interface vip
| ID | Block | Maturity |
|---|---|---|
| of_vip_jtag_mon | JTAG monitor and protocol checker | simulated |
| of_vip_swd_mon | Serial Wire Debug monitor and protocol checker | planned |
| of_vip_swd_bfm | Serial Wire Debug bus functional model and agent | planned |